The present invention relates to an integrated semiconductor memory having memory cells that are combined to form addressable normal units and to form at least one redundant unit for replacing one of the normal units. The memory has an address bus to which an address can be applied, and a redundancy circuit, which is connected to the address bus, for selecting the redundant unit.
For the purpose of repairing faulty memory cells, integrated semiconductor memories generally have redundant units of memory cells that are able to replace normal units of memory cells containing faulty memory cells by addressing. In this context, the integrated memory is tested, for example using an external testing device or a self-test device, and the redundant elements are then programmed. For this, a redundancy circuit has programmable elements, for example in the form of laser fuses or electrically programmable fuses, which are used to store the address of a unit that needs to be replaced. The programmable elements are programmed using a laser beam or a so-called burning voltage, for example in the course of the production process of the memory.
During the operation of the semiconductor memory, the normal units that need to be replaced are replaced, by addressing, the appropriate redundant units in the course of a memory access operation. At the start of the memory access operation, redundancy evaluation is carried out in the redundancy circuits within a selected memory area. To this end, by way of example, an address for the selected normal unit is applied to an address bus, and the applied address is then compared with an address for a faulty normal unit, which is stored in the respective redundancy circuit. Following the comparison, each of the redundancy circuits supplies a signal containing information about whether the applied address matches the address stored in the respective redundancy circuit. If there is a match, the appropriate redundancy circuit selects the associated redundant unit.
So that faulty normal units of memory cells in a semiconductor memory are replaced only by fault-free redundant units, it is expedient for not only the normal units of memory cells but also the redundant units of memory cells to be tested to ensure that they are free from faults. Such a test should be carried out before the programmable elements of the redundancy circuits are programmed by a laser, for example. In general, additional circuit complexity on the semiconductor memory is required for carrying out the test mode. In this case, it is beneficial for the additionally required circuit complexity to be comparatively low, in the interests of a low space requirement on the semiconductor memory.
It is accordingly an object of the invention to provide an integrated semiconductor memory with redundant units for memory cells which overcomes the above-mentioned disadvantages of the prior art devices of this general type, in which a redundant unit of memory cells can be tested and in which the circuit complexity required for this is comparatively low.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated semiconductor memory. The memory contains memory cells which are combined to form addressable normal units and further memory cells which are combined to form at least one redundant unit for replacing one of the addressable normal units. An address bus to which an address can be applied and has connection points is provided. A redundancy circuit is connected to the address bus and stores the address for one of the addressable normal units which is to be replaced by the redundant unit, the redundancy circuit having inputs and compares the address on the address bus with a stored address. The redundancy circuit selects the redundant unit if a match is established between the stored address and the address on the address bus. A processing unit is provided and has a first input connected to one of the connection points of the address bus, a second input receiving a test signal, and an output connected to one of the inputs of the redundancy circuit. The processing unit modifies an address signal only for a defined state of the test signal.
The object is achieved by an integrated semiconductor memory having memory cells that are combined to form addressable normal units. Further memory cells are combined to form at least one redundant unit for replacing one of the normal units. An address bus is provided to which an address can be applied. A redundancy circuit is provided, which is connected to the address bus, for storing an address for the normal unit that needs to be replaced by the redundant unit. The redundancy circuit compares the address that is on the address bus with the stored address, and selects the redundant unit if a match is established. A processing unit whose input is connected to a connection of the address bus and to a connection for a test signal is provided. The processing unit has an output connected to an input of the redundancy circuit, and which modifies an address signal only for a defined state of the test signal.
In the semiconductor memory according to the invention, existing address lines are used to select the redundant unit of memory cells during a test mode. In the case of such a redundancy test configuration, there is no need for, by way of example, an additional decoder or an additional selection line selecting the redundant unit of memory cells. To select the redundant unit in the test mode, the address lines and also the redundancy circuit that is likewise present are used. The redundancy circuit has not (yet) been programmed for the purpose of testing the redundant unit. The processing unit connected upstream of the redundancy circuit does not modify an address signal present at the input of the redundancy circuit in normal operation. An appropriate test signal modifies an address signal in the test mode only. In one simple embodiment, the processing unit may be in the form of a logic gate, for example. The additional circuit complexity required for the test mode is thus comparatively low.
The invention is suitable for any semiconductor memories in which faulty units of memory cells are repaired using redundant units of memory cells. The normal units are, by way of example, regular word lines or bit lines, and the redundant units are redundant word lines or bit lines. However, instead of replacing individual word lines or bit lines, it is also possible to replace larger units of memory cells, for example individual memory cell blocks, with appropriate redundant units.
In accordance with an added feature of the invention, the address on the address bus contains a plurality of address bits. Each of the connection points of the address bus is provided for each of the address bits. Each of the inputs of the redundancy circuit is provided for each of the address bits. The processing unit is connected to one of the connection points of the address bus and to one of the inputs of the redundancy circuit.
In accordance with an additional feature of the invention, the redundancy circuit contains memory circuits according to a number of the address bits, each of the memory circuits has a programmable element and at least one input connected to one of the inputs of the redundancy circuit.
In accordance with a further feature of the invention, the redundancy circuit has a further memory circuit with a programmable element, the further memory circuit contains information about whether information stored in the memory circuits is valid.
In accordance with another feature of the invention, the further memory circuit has at least one input receiving the test signal.
In accordance with a further added feature of the invention, each of the memory circuits and the further memory circuit has a first input for a logic signal and a second input for a complementary logic signal which is complementary to the logic signal.
In accordance with another added feature of the invention, each of the memory circuits has a respective output for an output signal which has a state of the complementary logic signal when the programmable element has been programmed, and a state of the logic signal when the programmable element has not been programmed.
In accordance with another additional feature of the invention, the programmable element contains a laser fuse.
In accordance with a concomitant feature of the invention, the redundant unit is one of a plurality of redundant units for replacing the normal units. The processing unit is one of a plurality of processing units. The redundancy circuit is one of a plurality of redundancy circuits, each of the redundancy circuits has an associated one of the processing units. The processing units are each connected to a different one of the connection points of the address bus and are each connected to a different one of the inputs of the redundancy circuits.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an integrated semiconductor memory with redundant units for memory cells, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.